Implementing Click IP Router Kernel on VLIW Architectures

In this work, we implemented the Click IP Router Kernel in C language provided by Scott Webber et al. for two VLIW processors designed for DSP purpose, namely the Philips Trimedia TM1300 processor and Texas Instrument TMS320C6701 processor. The performance of these processors are compared with those of three other processors, ARM SA-110, HPL-PD EPIC, and Intel IXP1200 [1]. Ways of further performance optimization is explored on both processors by using techniques such as function inlining, loop unrolling, and grafting. Introduction The very long instruction word (VLIW) architecture is considered to be one of the promising methods of increasing performance beyond standard RISC architectures. Although RISC architectures take advantage of temporal parallelism (by using pipelined functional units), VLIW architectures can also take advantage of spatial parallelism by using multiple functional units to execution several operations concurrently. Similar to superscalar architecture, the VLIW architecture can reduce the clock per instruction (CPI) factor by executing several operations concurrently. Compare to superscalar architecture, VLIW has the advantage of simplified hardware for decoding and issuing instructions. Since it is easier to exploit the instruction level parallelism (ILP) in the stream, it is currently found more successful in the DSP applications. Networking protocol application is also one of the applications where the ILP can be explored. In this study, we will explore the performance of the two VLIW architectures: the latest Philips Trimedia and TI TMS320C6701 processors, by implementing an IP routing kernel. The results are also compared with other architectures. It shows that the VLIW architecture has the performance advantage over the standard RISC architecture. However, it is not as good as dedicated networking protocol processor such as Intel's IXP1200. The following section will briefly introduce the Click IP router program we implemented. Then the performance and optimization on both Trimedia TM1300 and TI TMS320C6701 will be described in detail. Click IP Router Kernel Click is a modular software router developed by Parallel and Distributed Operating System group of MIT. Its main advantage is in its modular structure and standard language implementation. These features greatly simplify the configuration process and make the router scalable. In this project, only a very simple kernel of an IP router is implemented as shown in Fig. 1. The first element, which is the basic building block in Click, is used to strip off the useless information, such as Ethernet header, from the beginning of the packet. Then the stripped packet is passed on to the CheckIPHeader element. This element will check the validity of the IP header. Invalid packets are dropped if no disposal port is used. Then the following element GetIPAddress will copy the IP address of this packet to the destination IP address annotation for use by other elements. The final stage of the kernel is the LookupIPRoute stage, where the destination IP address annotation is checked and the destination gateway is write into the destination annotation and. Then the packet is send to the right port corresponding to the gateway. A separate random traffic generator program Fig. 1 Illustration of the Click router elements generates the packets used for performance evaluation. Philips Trimedia TM1300